The present invention relates to the interconnection structure for data exchange between the various addressable elements of a microcomputer, more particularly to the microcomputer of an active implantable medical device such as a pacemaker or a cardiac defibrillator.
The energy consumption of the microcomputer is a factor which must carefully be controlled in battery operated devices, such as active implantable medical devices. This is because it has a direct impact on the service life of the implant, i.e., the number of years until the devices reaches the end of its useful life when a surgical intervention will be necessary to change the implant.
In this regard, the use of increasingly complex microcomputer structures has led to an increase on the microcircuit (integrated circuit) of read-write memories (RAMs), read only memories (ROMs), data registers, direct memory access (DMA), interrupt control elements, etc. (hereinafter collectively and generically referred to as xe2x80x9caddressable element(s)xe2x80x9d of the microcomputer).
These various addressable elements are inter-connected to allow data exchange therebetween. This occurs by means of a structure, including a common interconnection artery, ensuring a parallel transfer, over a group of conductors, of the information to be exchanged. The typical structure of such an interconnection artery is that of the bi-directional bus to which all the elements of the microcomputer are connected. The data exchange can take place in one direction, for example, from the central processing unit towards a memory for a write instruction, or in the opposite direction, for example, from a memory towards the central processing unit for a read instruction. The multiplication (increase) of the number of addressable elements connected to such a bi-directional data bus brings with it, however, a certain number of difficulties, which have a serious consequence on energy consumption, a critical factor in the field of implanted medical devices, as noted above.
First, a bi-directional bus connected to many addressable elements implies, from the electronic point of view, a large parasitic capacitor connected to ground. This parasitic capacitor on the one hand will increase the time necessary to modify the logical state of the conductors of common interconnection artery. This is because the relatively greater time necessary to load each of the bus conductors leads to more bus data transfer cycles, and to transfer cycles which are longer. In addition and especially, the charge and the discharge of this capacitor with each change of the logical state will appreciably increase the power consumption of the circuit.
Various solutions have been proposed to cure this disadvantage, for example, by increasing the size of the bus conductors to be able to charge and discharge more quickly the parasitic capacitor. But the increase in the conductor size induces an even larger capacitor, and is moreover made to the detriment of the surface area of the integrated circuit. This is a particularly annoying consequence in the case of implantable medical devices, for which miniaturization is particularly important.
Another disadvantage is that each addressable element receives transition signals from the bi-directional bus, which implies a useless energy consumption. A possible solution consists of dividing the bi-directional bus in a multitude of bi-directional sub-buses. This solution suffers the disadvantage from the point of view of the routing of conductors, i.e., to the detriment of surface area used. To remain compatible with the imposed cycle times, the controllers for the bus conductors are activated with a certain overlapping period which corresponds to short-circuits, and this is done at the cost of a transitory increase in the power consumption of the circuit.
In addition, the bi-directional bus conductors have one of three states, namely, xe2x80x981xe2x80x99, xe2x80x980xe2x80x99, and a state with high impedance. The latter state corresponds to an absence of transmission data on the bus, i.e., a state not controlled. In microcomputers with low current consumption, in particular those which inhibit or otherwise reduce the operation of the clock system to save energy, it is essential that the circuit does not cease functioning at the time when a segment of bus is in a state with high impedance, because floating inputs on CMOS circuits would lead to high currents. This is contrary to the desired results of saving energy and reducing current. To prevent this, one can place on the bus clamping circuits or repeater circuits, which maintain the state of the bus in the absence of any control. These circuits make it possible to avoid any floating input, but nevertheless consume energy for their update, with each transaction occurring on the bus.
It is, therefore, an object of the present invention to overcome the aforementioned disadvantages, by proposing an interconnection structure which minimizes, if not avoids, the recourse to a bi-directional bus.
It is another object of the invention to provide an interconnected structure which is well suited to complex miniaturized circuits having low current consumption.
Broadly, the present invention provides an interconnection structure which includes an interconnection artery, ensuring the parallel transfer of information to be exchanged over a group of conductors, configured in at least one ring on which information circulates in a closed loop and in a one-way direction, this artery comprising at least one coupling point to an addressable element of the microcomputer, more preferably a plurality of coupling points between the ring and the various addressable elements of the microcomputer.
In one embodiment, at least some of the coupling points include a gateway circuit connecting one ring to another ring of a lower order, on which lower order ring information also circulates in a closed loop and in a one way-direction. The gateway thus provides for a transfer of data between the coupled rings, which in combination can comprise a structure comprising a plurality of ordered rings having a hierarchy between them.
In this embodiment, it is in particular envisaged that the ring of the highest order will have one coupling point connecting it to a central processing unit of the device, more particularly to the central processing device which controls the treatment (therapeutic or diagnostic) of an active implantable medical device.
In addition, the gateway circuit between rings advantageously includes one or more multiplexers to transfer selectively downstream from the higher order ring, either the information received from the lower order ring, if the coupling point corresponding to the addressed element is on the lower order ring, or a ring of a still lower order coupled to the former lower order ring, or otherwise the information is received from a higher order ring upstream.
Advantageously, at least some of the coupling points include a register associated with the corresponding microcomputer addressable element, and more preferably also include a multiplexing means to transfer selectively downstream from the ring either the contents of the register, if the coupling point corresponds to the addressed element, or otherwise the information received from the ring upstream.
In one embodiment, one of the coupling points can be a coupling point to a bi-directional data exchange bus, this coupling point being then preferably located on a higher order ring and immediately preceding in the direction of flow of information the central processing unit (CPU) on this ring.
Preferably, the interconnection artery conductors of the rings operate with two-level logic, and without any high impedance state.
Preferably also, the microcomputer circuit presents a topology of implementation in which, for each of the rings, the elements belonging to the same ring are gathered (laid out in silicon) in proximity on a common field, and the fields corresponding to the different rings are in turn laid out adjacent to one another, immediately following or preceding one another, according to the direction of information flow.
Advantageously, in accordance with the present invention, the abandonment of bi-directional bus architecture as the backbone artery of data exchange, and in particular the state with high impedance, will allow, to greatly reduce the parasitic capacitor with its noted disadvantages, and avoid the problems associated with the presence of transitions from one direction to the other on the bus.
Among the other advantages obtained by the invention are: (1) less current (energy) consumption for the same topology of circuit (i.e., for the same number of different interconnected addressable elements); (2) the possibility of reducing the cycle time, thereby to increase the processing speed of the data manipulation; and (3) improving the topology of circuit to gain surface area for additional circuits and functionality or to increase the miniaturization of circuit.